Integrated circuits including magneto-resistive memory cells are known. A magneto-resistive memory cell generally includes a memory element comprising a reference layer, a barrier layer, and a free layer which are stacked above each other in this order. Each of the reference layer, the barrier layer, and the free layer may comprise multiple sublayers. It is becoming more and more difficult to manufacture integrated circuits of high reproducibility due to the increased memory density of the magneto-resistive memory cells.
FIG. 1 shows a first manufacturing stage 100 of a conventional method of manufacturing an integrated circuit having a plurality of magneto-resistive memory cells. The manufacturing stage 100 is obtained after having stacked a reference layer 102, a barrier layer 104 and a free layer 106 in this order above each other.
FIG. 2 shows a conventional manufacturing stage 200 obtained after having deposited a masking layer 108 on the free layer 106. The masking layer 108 has been patterned. Further, the patterned masking layer 108 has been used in order to pattern the free layer 106, the barrier layer 104, and the reference layer 102 into magnetic tunneling junction stacks 110 which are laterally separated against each other, i.e., the full stack of layers shown in FIG. 1 has been patterned. Each magnetic tunneling junction stack 110 can be interpreted as a memory element of a magneto-resistive memory cell.
The magnetic tunneling junction stacks 110 thus obtained may be electrically connected as shown in FIG. 3. That is, the top end of each magnetic tunneling junction (MTJ) stack 110 is connected to a bit line 112, and the bottom end of each magnetic tunneling junction stack 110 is connected to a select device 114. Here, it is assumed that the select device 114 is a field effect transistor, the gate of which being connected to a word line 116, the source of which being connected to a source line 118, and the drain of which being connected to the bottom end of the magnetic tunneling junction stack 110. Here, it is assumed that the masking layer 108 is conductive (i.e., it is not removed after the patterning process).
FIG. 4 shows the equivalent circuit of the integrated circuit shown in FIG. 3. As can be derived from FIG. 4, each magnetic tunneling junction stack can be represented by a resistance 120.